Testbench Tool 2.01
Full Circuit releases greatly enhanced 'TestBench Tool':
Easily create testbenches (VHDL) with this low cost but powerful tool.
AUTOMATIC
Extracts entity from VHDL source and creates testbench VHDL source. Fills in signal names on tool so that all the user has to do is construct the test patterns.
FAST
Testbench VHDL source is not changed each time a test is revised (Test patterns are saved to a test vector file) so VHDL is only compiled once.
POWERFUL
Supports complex formulae for describing signal relationships. Has repeat sub section and repeat section. Text entry and plot view. Description displays in simulator as each test is executed.
MODULAR
Tests can be constructed in sections and test vectors built from one or all sections.
FLEXIBLE
Testbench source is small and simple to allow easy user enhancement. User modifications are protected from change by tool. User can modify project testbench for local changes or template testbench for global changes (i.e. adding user functions).
Test vectors are not limited just to entity signals but can include variables and times. A typical use of this would be to pulse a clock line N times rather than have N vector file entries. Note that the clock line can still be a signal so the vectors can drive the clock directly at the change over for better control (i.e. use N-1 in variable). Another use could be to supply data where source is incomplete
LOW COST
80 GBP (+VAT if applicable). Demo and 30 day full functional trial version available.
Note requires Excel 97 or greater.
SCREENSHOTS and WORKED EXAMPLE
www.fullcircuit.com/TBtool.htm or www.fullcircuit.com (for site navigation menu and other items)
| Dialup | (56k) | 31 s |
| ISDN | (128k) | 14 s |
| DSL | (512k) | 04 s |
| Cable | (1024k) | 02 s |
| T1 | (1484k) | 02 s |
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